1. Technical Field
The present disclosure relates to the field of semiconductor technology, and more particularly to a fin-type field effect transistor and manufacturing method thereof.
2. Description of the Related Art
The transistor is a key component in modern integrated circuits. To meet increasing demands on device speed and performance, the drive current of the transistor needs to increase. Since the drive current is proportional to a gate width of the transistor, it is preferable that the transistor has a larger gate width.
However, the increase in gate width is incompatible with the scaling (reduction) in device size. The fin-type field effect transistor (FinFET) has been developed to address the above problem. In a conventional FinFET manufacturing process, a thin “fin” (or fin member) is formed extending from a substrate. For example, the fin may be formed by etching in a silicon substrate. Specifically, a vertical fin-like member may be formed in a channel of the FinFET. A gate electrode may be provided on the fin-shaped member (e.g., surrounding the fin-shaped member). In some instances, the gate electrode may be disposed on one side of the channel. In other instances, the gate electrode may be disposed on both sides of the channel (which allows the gate to control the channel from both sides of the channel).
FinFET devices have many advantages such as reduced short channel effect and increased current flow. However, to reduce transistor leakage current (or increase isolation between n-type and p-type FinFET device) in existing FinFET devices, the shallow trench isolation in the FinFET devices has to be modified. For example, one effective way is to increase the depth of the shallow trench isolation. However, as fin spacing continues to decrease, it becomes increasingly difficult to control the morphology of the fin-shaped member and the filling of the channel.
Another way to reduce transistor leakage current (or increase isolation between n-type and p-type FinFET device) is to increase the distance between devices. However, the increased device spacing will lead to larger area consumption.
Presently, the shallow trench isolation in FinFET can be improved by increasing the ion implantation dosage in the N-well (NW) and P-well (PW) of the FinFET. Some TOAD simulation results have shown that increasing the ion implantation dosage can increase the breakdown voltage (BVD) in the N+/NW and P+/PW. However, if the ion implantation dosage is greater than 1014/cm2, problems such as low resistance (Rs), increase in junction leakage current, and high junction capacitance may occur.